R8C-18_1 Datasheet, PDF (207/257 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MCU R8C FAMILY / R8C/1x SERIES

R8C/18 Group, R8C/19 Group
17. Flash Memory Version
17.4.4 Status Register
The status register indicates the operating status of the flash memory and whether an erase or
program operation has completed normally or in error. Status of the status register can be read by bits
FMR00, FMR06, and FMR07 in the FMR0 register.
Table 17.5 lists the Status Register Bits.
In EW0 mode, the status register can be read in the following cases:
• When a given address in the user ROM area is read after writing the read status register
command
• When a given address in the user ROM area is read after executing the program or block erase
command but before executing the read array command.
17.4.4.1 Sequencer Status (Bits SR7 and FMR00)
The sequencer status bits indicate the operating status of the flash memory. SR7 is set to 0 (busy)
during/auto-programming and auto-erasure, and is set to 1 (ready) at the same time the operation
completes.
17.4.4.2 Erase Status (Bits SR5 and FMR07)
Refer to 17.4.5 Full Status Check.
17.4.4.3 Program Status (Bits SR4 and FMR06)
Refer to 17.4.5 Full Status Check.
Table 17.5 Status Register Bits
Status Register Bit FMR0 Register Bit Status Name
Description
0
1
SR0 (D0)
−
Reserved
−
−
SR1 (D1)
−
Reserved
−
−
SR2 (D2)
−
Reserved
−
−
SR3 (D3)
−
Reserved
−
−
SR4 (D4)
FMR06
Program status Completed Error
normally
SR5 (D5)
FMR07
Erase status Completed Error
normally
SR6 (D6)
−
Reserved
−
−
SR7 (D7)
FMR00
Sequencer
Busy
Ready
status
Value after
Reset
−
−
−
−
0
0
−
1
• D0 to D7: Indicate the data bus which is read when the read status register command is executed.
• Bits FMR07 (SR5) to FMR06 (SR4) are set to 0 by executing the clear status register command.
• When the FMR07 bit (SR5) or FMR06 bit (SR4) is set to 1, the program and block erase commands
cannot be accepted.
Rev.1.30 Apr 14, 2006 Page 192 of 233
REJ09B0222-0130