TMS320C6745 Datasheet, PDF (204/209 Pages) Texas Instruments – Floating-point Digital Signal Processor

TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377A – SEPTEMBER 2008 – REVISED OCTOBER 2008
www.ti.com
7.2 Thermal Data for PTP
The following table(s) show the thermal resistance characteristics for the HTQFP–PTP mechanical
package.
Table 7-2. Thermal Resistance Characteristics (HTQFP Package) [PTP]
NO.
°C/W ⁽¹⁾
°C/W ⁽²⁾
°C/W ⁽³⁾
°C/W ⁽⁴⁾
AIR FLOW
(m/s) ⁽⁵⁾
1 RΘ_JC
2 RΘ_JB
3 RΘ_JA
4
Junction-to-case
Junction-to-board
Junction-to-free air
7.8
9.4
8.6
10.1
N/A
6.2
9.9
7.1
10.6
N/A
21.3
27.9
23.2
30.6
0.00
14.3
20.2
22.6
0.50
5
6 ^{RΘJMA Junction-to-moving air}
13.1
18.6
12.1
17.4
21.0
1.00
19.6
2.00
7
11.2
16.2
18.2
4.00
8
0.5
0.7
0.8
0.00
9
0.6
0.9
1.0
0.50
10 Psi_JT
11
Junction-to-package top
0.7
1.0
0.8
1.1
1.1
1.00
1.3
2.00
12
1.0
1.3
1.5
4.00
13
6.3
9.5
10.8
0.00
14
5.9
8.8
9.9
0.50
15 Psi_JB
16
Junction-to-board
5.9
8.7
5.8
8.6
9.8
1.00
9.7
2.00
17
5.8
8.5
9.6
4.00
(1) Simulation data, using a model of a JEDEC defined 2S2P system with a 12mmx12mm copper pad on the top and bottom copper layers
connected with an 8x8 thermal via array and soldered to the package thermal pad. Power dissipation of 1W assumed, 70C Ambient
temp assumed. Signal layer copper coverage 20%, inner layer copper coverage 90%. Actual performance will change based on
environment as well as application. For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal
Test Method Environment Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for
Leaded Surface Mount Packages.
(2) Simulation data, using the same model but with 1oz (35um) top and bottom copper thickness and 0.5oz (18um) inner copper thickness.
Power dissipation of 1W and ambient temp of 70C assumed.
(3) Simulation data, 1S1P PCB model with 12x12mm copper pad on the top layer soldered to device thermal pad and connected to the
bottom copper layer (90% copper) with an 8x8 thermal via array. Power dissipation of 1W and ambient temp of 70C assumed. Copper
thickness 2oz (70um) top and bottom.
(4) Simulation data, 1S1P PCB model with 12x12mm copper pad on the top layer soldered to device thermal pad and connected to the
bottom copper layer (90% copper) with an 8x8 thermal via array. Power dissipation of 1W and ambient temp of 70C assumed. Copper
thickness 1oz (35um) top and bottom.
(5) m/s = meters per second
7.3 Mechanical Drawings
This section contains mechanical drawings for the ZKB Ball Grid Array package and the PTP Thin Quad
Flat Pack package. Additionally, for the PTP package a detailed drawing of the actual thermal pad
dimensions as well as a recommended PCB footprint are provided.
204 Mechanical Packaging and Orderable Information
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