SN74AUP2G08 Datasheet, PDF (2/15 Pages) Texas Instruments – LOW-POWER DUAL 2-INPUT POSITIVE-AND GATE

SN74AUP2G08
LOW-POWER DUAL 2-INPUT POSITIVE-AND GATE
SCES681A – JANUARY 2008 – REVISED JANUARY 2008
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This dual 2-input positive-AND gate performs the Boolean function Y + A • B or Y + A ) B in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
T_A
–40°C to 85°C
ORDERING INFORMATION
PACKAGE ^{(1) (2)}
ORDERABLE PART NUMBER TOP-SIDE MARKING⁽³⁾
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YFP
Reel of 3000
SN74AUP2G08YFPR
_ _ _ HE_
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000
SN74AUP2G08YZPR
_ _ _ HE_
QFN – RSE
Reel of 3000
SN74AUP2G08RSER
HE
VSSOP – DCU
Reel of 3000
SN74AUP2G08DCUR
H08_
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(3) YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
DCU – The actual top-side marking has one additional character to denote assembly/test site.
FUNCTION TABLE
INPUTS
A
B
L
L
L
H
H
L
H
H
OUTPUT
Y
L
L
L
H
LOGIC DIAGRAM (POSITIVE LOGIC)
1
1A
2
1B
7 _1Y
5
2A
6
2B
Pin numbers shown are for DCU, YFP, and YZP packages.
3
2Y
2
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