SN74AUP2G08 Datasheet, PDF (1/15 Pages) Texas Instruments – LOW-POWER DUAL 2-INPUT POSITIVE-AND GATE

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SN74AUP2G08
LOW-POWER DUAL 2-INPUT POSITIVE-AND GATE
SCES681A – JANUARY 2008 – REVISED JANUARY 2008
FEATURES
1
•2 Available in the Texas Instruments NanoFree™
Package
• Low Static-Power Consumption
(I_CC = 0.9 µA Max)
• Low Dynamic-Power Consumption
(C_pd = 4.3 pF Typ at 3.3 V)
• Low Input Capacitance (C_i = 1.5 pF Typ)
• Low Noise – Overshoot and Undershoot
<10% of V_CC
• I_off Supports Partial-Power-Down Mode
Operation
• Schmitt-Trigger Action Allows Slow Input
Transition and Better Switching Noise
Immunity at the Input
(V_hys = 250 mV Typ at 3.3 V)
• Wide Operating V_CC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
• t_pd = 4.3 ns Max at 3.3 V
• Suitable for Point-to-Point Applications
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCU PACKAGE
(TOP VIEW)
RSE PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
YFP PACKAGE
(BOTTOM VIEW)
1A
1B
2Y
GND
1
8
P^{342 REVIE576W}
V_CC
1Y
2B
2A
GND 4 5 2A
2Y 3 6 2B
1Y
2B
2A
P321 ^RE84VIE756W
1A
1B
2Y
1B 2 7 1Y
1A
18
V_CC
GND 4 5 2A
2Y 3 6 2B
1B 2 7 1Y
1A 1 8 V_CC
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire V_CC range
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal
integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
Static-Power Consumption
(µA)
Dynamic-Power Consumption
(pF)
100%
100%
80%
80%
60%
40%
3.3-V
Logic^†
60%
40%
3.3-V
L^Lo^Vg^Cic^†
20%
20%
0%
AUP
0%
AUP
† _{Single, dual, and triple gates}
Figure 1. AUP – The Lowest-Power Family
Switching Characteristics
at 25 MHz^†
3.5
3
2.5
2 ^Input
1.5
1
Output
0.5
0
−0.5
0
5
10 15 20 25 30 35 40 45
Time − ns
† _{AUP1G08 data at CL = 15 pF}
Figure 2. Excellent Signal Integrity
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
2
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated