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NP90N04VUK_15 Datasheet, PDF (2/8 Pages) Renesas Technology Corp – MOS FIELD EFFECT TRANSISTOR
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NP90N04VUK
Electrical Characteristics (TA = 25°C)
Item
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Threshold Voltage
Forward Transfer Admittance *1
Drain to Source On-state Resistance *1
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage *1
Reverse Recovery Time
Reverse Recovery Charge
Note: *1 Pulsed test
Symbol
IDSS
IGSS
VGS(th)
| yfs |
RDS(on)
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QG
QGS
QGD
VF(S-D)
trr
Qrr
MIN.
—
—
2.0
30
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TYP.
—
—
3.0
60
2.35
3900
530
200
25
12
65
8
68
18
18
0.9
47
68
MAX.
1
100
4.0
—
2.80
5850
800
360
60
30
130
20
102
—
—
1.5
—
—
Unit
A
nA
V
S
m
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
Test Conditions
VDS = 40 V, VGS = 0 V
VGS = 20 V, VDS = 0 V
VDS = VGS, ID = 250 A
VDS = 5 V, ID = 45 A
VGS = 10 V, ID = 45 A
VDS = 25 V
VGS = 0 V
f = 1 MHz
VDD = 20 V, ID = 45 A
VGS = 10 V
RG = 0 
VDD = 32 V
VGS = 10 V
ID = 90 A
IF = 90 A, VGS = 0 V
IF = 90 A, VGS = 0 V
di/dt = 100 A/s
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
L
PG.
VGS = 20 → 0 V
50 Ω
VDD
BVDSS
ID IAS
VDD
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
PG.
RG
VGS
0
τ
τ = 1 μs
Duty Cycle ≤ 1%
RL
VGS
VGS
Wave Form
10%
0
VDD
VDS
90%
VDS
VDS
0
Wave Form
td(on)
VGS
90%
90%
10% 10%
tr td(off)
tf
ton
toff
R07DS0577EJ0100 Rev.1.00
Nov 29, 2011
Page 2 of 6
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