NP50P04SLG_15 Datasheet, PDF (2/8 Pages) Renesas Technology Corp – MOS FIELD EFFECT TRANSISTOR

NP50P04SLG
Electrical Characteristics (T_A = 25°C)
Item
Symbol Min
Zero Gate Voltage Drain Current I_DSS
Gate Leakage Current
Gate to Source Threshold
Voltage
Forward Transfer Admittance ^∗1
I_GSS
V_GS(th)
| y_fs |
−1.0
12
Drain to Source On-state
Resistance ^∗1
R_DS(on)1
R_DS(on)2
Input Capacitance
C_iss
Output Capacitance
C_oss
Reverse Transfer Capacitance C_rss
Turn-on Delay Time
t_d(on)
Rise Time
t_r
Turn-off Delay Time
t_d(off)
Fall Time
t_f
Total Gate Charge
Q_G
Gate to Source Charge
Q_GS
Gate to Drain Charge
Body Diode Forward Voltage ^∗1
Q_GD
V_F(S-D)
Reverse Recovery Time
t_rr
Reverse Recovery Charge
Q_rr
Note: ^∗1. Pulsed test PW ≤ 350 μs, Duty Cycle ≤ 2%
Typ
−1.4
44
8.2
9.8
3800
740
500
11
15
250
150
100
13
30
0.96
50
63
Max
−1
m10
−2.5
9.6
15
5700
1120
905
24
39
505
380
150
1.5
Chapter Title
Unit
μA
μA
V
Test Conditions
VDS = −40 V, VGS = 0 V
VGS = m20 V, VDS = 0 V
VDS = VGS, ID = −250 μA
S
VDS = −10 V, ID = −25 A
mΩ VGS = −10 V, ID = −25 A
mΩ VGS = −4.5 V, ID = −25 A
pF
VDS = −10 V,
pF
VGS = 0 V,
pF f = 1 MHz
ns
VDD = −20 V, ID = −25 A,
ns
VGS = −10 V,
ns
RG = 0 Ω
ns
nC
VDD = −32 V,
nC
VGS = −10 V,
nC
ID = −50 A
V
IF = −50 A, VGS = 0 V
ns
IF = −50 A, VGS = 0 V,
nC di/dt = −100 A/μs
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = −20 → 0 V
−
IAS ^BVDSS
VDS
ID
VDD
Starting Tch
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG
PG.
VGS(−)
0
τ
τ = 1 μs
Duty Cycle ≤ 1%
RL
VDD
VGS(−)
VGS
Wave Form
0 ^10%
VDS(−)
90%
VDS
VDS
Wave Form ⁰
td(on)
VGS
90%
90%
10% 10%
tr td(off)
tf
ton
toff
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = −2 mA
RL
PG.
50 Ω
VDD
R07DS0241EJ0100 Rev.1.00
Feb 09, 2011
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