HD74LV10A Datasheet, PDF (2/8 Pages) Hitachi Semiconductor – Triple 3-input Positive NAND Gates

HD74LV10A
Pin Arrangement
1A 1
1B 2
2A 3
2B 4
2C 5
2Y 6
GND 7
(Top view)
14 VCC
13 1C
12 1Y
11 3C
10 3B
9 3A
8 3Y
Absolute Maximum Ratings
Item
Symbol Ratings
Unit
Conditions
Supply voltage range
Input voltage range*¹
Output voltage range*^{1, 2}
Input clamp current
Output clamp current
Continuous output current
Continuous current through
V_CC or GND
Maximum power dissipation at
Ta = 25°C (in still air)*³
V_CC
V_I
V_O
I_IK
I_OK
I_O
I_CC or I_GND
–0.5 to 7.0
–0.5 to 7.0
–0.5 to V_CC + 0.5
–0.5 to 7.0
–20
±50
±25
±50
P_T
785
500
V
V
V
Output: H or L
V_CC: OFF
mA
V_I < 0
mA
V_O < 0 or V_O > V_CC
mA
V_O = 0 to V_CC
mA
mW
SOP
TSSOP
Storage temperature
Tstg
–65 to 150
°C
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
1. The input and output voltage ratings may be exceeded even if the input and output clamp-current ratings are
observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Rev.3.00, May 24, 2004, page 2 of 7