HD74HC95 Datasheet, PDF (2/7 Pages) Hitachi Semiconductor – 4-bit Parallel Access Shift Register

HD74HC95
Function Table
Inputs
Clocks
Parallel
Outputs
Mode Control 2 (L) 1 (R) Serial A
B
C
D
QA
QB
QC
QD
H
H
X
X
X
X
X
X
QA0
QB0
QC0
QD0
H
X
X
a
b
c
d
a
b
c
d
H
X
X
QB+
QC+
QD+
d
QBn
QCn
QDn
d
L
L
H
X
X
X
X
X
QA0
QB0
QC0
QD0
L
X
L
X
H
X
X
X
X
H
QAn
QBn
QCn
L
X
X
X
X
L
QAn
QBn
QCn
L
L
X
X
X
X
X
QA0
QB0
QC0
QD0
L
L
X
X
X
X
X
QA0
QB0
QC0
QD0
L
H
X
X
X
X
X
QA0
QB0
QC0
QD0
H
L
X
X
X
X
X
QA0
QB0
QC0
QD0
H
H
X
X
X
X
X
QA0
QB0
QC0
QD0
Notes: 1. H : High level, L : Low level, X : Irrelevant
2. a to d : The level of steady-state input at inputs A, B, C or D respectively
3. QA0 to QD0 : The level of QA, QB, QC or QD respectively before the indicated steady-state input conditions were
established.
4. QAn to QDn : The level of QA, QB, QC or QD respectively before the most-recent ( ) transition of the clock.
5. + : Shifting left requires external connection of QB to A, QC to B and QD to C. Serial data is entered at input D.
Pin Arrangement
Serial
Input
1
A2
B3
Inputs
C4
D5
Mode
Control
6
GND 7
Serial
A _Input QA
B
QB
C
QC
D
QD
Mode CK1
CK2
(Top View)
14 Vcc
13 QA
12 QB
Outputs
11 QC
10 QD
9
Clock1
R-Shift
8 ^Clock2
L-Shift
(Load)
Rev.2.00, Oct 06, 2005 page 2 of 6