HD74HC95 Datasheet, PDF (1/7 Pages) Hitachi Semiconductor – 4-bit Parallel Access Shift Register

HD74HC95
8-bit Shift Register
REJ03D0558-0200
(Previous ADE-205-431)
Rev.2.00
Oct 06, 2005
Description
This 4-bit register features parallel and serial inputs, parallel outputs, mode control, and two clock inputs. The register
has three mode operation:
• Parallel (broadside) load
• Shift right (the direction Q_A toward Q_D)
• Shift left (the direction Q_D toward Q_A)
Parallel loading is accomplished by applying the four bits of data and taking the mode control input high. The data is
loaded into the associated flip-flops and appears at the outputs after the high-to-low transition of the clock-2 input.
During loading, the entry of serial data is inhibited. Shift right is accomplished on the high-to-low transition of clock-1
when the mode control is low; shift left is accomplished on the high-to-low transition of clock-2 when the mode control
is high by connecting the output of each flip-flop (Q_D to input C, etc.) and serial data is entered at input D. The clock
input may be applied commonly to clock-1 and clock-2 if both modes can be clocked from the same source. Changes at
the mode control input should normally be made while both clock inputs are low: however, conditions described in the
last three lines of the function table will also ensure that register contents are protected.
Features
• High Speed Operation: t_pd (Clock to Q) = 17 ns typ (C_L = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: V_CC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: I_CC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HC95P
DILP-14 pin
PRDP0014AB-B _P
(DP-14AV)
HD74HC95RPEL
SOP-14 pin (JEDEC)
PRSP0014DE-A
(FP-14DNV)
RP
Taping Abbreviation
(Quantity)
—
EL (2,500 pcs/reel)
Rev.2.00, Oct 06, 2005 page 1 of 6