HD74HC259 Datasheet, PDF (2/10 Pages) Hitachi Semiconductor – 8-bit Addressable Latch

HD74HC259
Function Table
Inputs
Clear
G
H
L
H
H
L
L
L
H
Output of Addressed
Latch
D
Qio
D
L
Each Other Output
Function
Qio
Addressable latch
Qio
Memory
L
8-line demultiplexer
L
Clear
Select Inputs
Latch Addressed
C
B
A
L
L
L
0
L
L
H
1
L
H
L
2
L
H
H
3
H
L
L
4
H
L
H
5
H
H
L
6
H
H
H
7
Notes: 1. D: the level at the data input
2. Qio: the level of Qi (i = 0, 1, ···7, as appropriate) before the indicated steady-state input conditions were
established.
Pin Arrangement
Latch
select
A1
B2
C3
Q0 4
Outputs
Q1 5
Q2 6
Q3 7
GND 8
A
B
CLR
C
G
Q0
D
Q1
Q7
Q2
Q6
Q3 _Q4 Q5
16 VCC
15 Clear
14 Enable
13
Data
input
12 Q₇
11 Q₆
10 Q₅
Outputs
9 Q₄
(Top view)
Rev.2.00 Jan 31, 2006 page 2 of 9