HD74HC194 Datasheet, PDF (2/9 Pages) Hitachi Semiconductor – 4-bit Bidirectional Universal Shift Register

HD74HC194
Function Table
Inputs
Operating
Outputs
Mode
Clear
Mode
Clock
Serial
Parallel
S₁
S₀
Shift Left Shift Right A B C D Q_A Q_B Q_C Q_D
Clear
L
X
X
X
X
X
XXXX
L
L
L
L
Parallel load H H H
X
X
abcd a
b
c
d
Shift right
HLH
X
HLH
X
Shift left
HH L
H
HH L
L
Hold
H
L
L
X
X
H
X
X
L
X
HXXH
X
H : high level (Steady state)
H
X
X
X
X
H
Q_An Q_Bn Q_Cn
L
XXXX
L
Q_An Q_Bn Q_Cn
X
X
X
X
X Q_Bn Q_Cn Q_Dn H
X
X
X
X
X Q_Bn Q_Cn Q_Dn
L
X
X
X
X
X Q_A0 Q_B0 Q_C0 Q_D0
X
X
X
X
X Q_A0 Q_B0 Q_C0 Q_D0
X
X
X
X
X Q_A0 Q_B0 Q_C0 Q_D0
L : low level (Steady state)
X : don’t care
: transition from low to high level.
a, b, c, d : the level of steady-state input at inputs A, B, C or D respectively.
Q_A0, Q_B0, Q_C0, Q_D0 : the level of Q_A, Q_B, Q_C or Q_D respectively, before the indicated steady-state input conditions were
established.
Q_An, Q_Bn, Q_Cn, Q_Dn :
the level of Q_A, Q_B, Q_C or Q_D respectively before the most recent transition of the clock.
Pin Arrangement
Clear 1
Shift
Right ₂
Serial-Input
A3
B4
Parallel
Inputs _{C 5}
D6
Shift
Left 7
Serial-Input
GND 8
R ^CLR QA
A
QB
B
QC
C
QD
D
CK
L
S1
S0
(Top view)
16 V_CC
15 QA
14 QB
Parallel
13 QC ^Outputs
12 QD
11 Clock
10 S1
Mode Control
9 S0
Rev.2.00 Jan 31, 2006 page 2 of 8