HM64YLB36512_15 Datasheet, PDF (19/33 Pages) Renesas Technology Corp – 16M Synchronous Late Write Fast Static RAM (512-kword × 36-bit)

HM64YLB36512 Series
Write Cycle
t_KHKH
t_KHKL
t_KLKH
K, K
t_AVKH
t_KHAX
SA
A1
A2
A3
A4
t_AVKH
t_KHAX
SS
SWE
t_AVKH
t_KHAX
SWEx
t_AVKH
t_KHAX
G
t_DVKH
t_KHDX
DQ
D0
D1
D2
D3
Notes: ZZ = V_IL, x: a to d
Write operation (late write and late select mode)
During write cycle, the write data follows the write address by one cycle. All N bits of address are presented during
the same cycle. Any subsequent read to this address should get the latest data. Because in the actual implementation
the data will be written into the SRAM array only after the next write address is received, a one-entry buffer is
needed to hold the write data and to allow bypassing of data from the write buffer to the output if there is a read of
the same address.
Rev.3.00 Jan 13, 2006 page 17 of 29