H8S-2668 Datasheet, PDF (177/667 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 6 Bus Controller (BSC)
Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the
system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in
figure 6.22. In this case, with the setting for no idle cycle insertion (a), there may be a period of
overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle
insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the
initial state after reset release, idle cycle insertion (b) is set.
φ
Address bus
CS (area A)
CS (area B)
RD
Bus cycle A Bus cycle B
T₁ T₂ T₃ T₁ T₂
φ
Address bus
CS (area A)
CS (area B)
RD
Bus cycle A
T₁ T₂ T₃
Bus cycle B
T_i T₁ T₂
Overlap period between CS (area B)
and RD may occur
(a) No idle cycle insertion
(ICIS1 = 0)
Idle cycle
(b) Idle cycle insertion
(ICIS1 = 1, initial value)
Figure 6.22 Relationship between Chip Select (CS) and Read (RD)
6.6.2 Pin States in Idle Cycle
Table 6.4 shows the pin states in an idle cycle.
Table 6.4 Pin States in Idle Cycle
Pins
A23 to A0
D15 to D0
CSn (n = 7 to 0)
AS
RD
HWR, LWR
Pin State
Contents of following bus cycle
High impedance
High
High
High
High
Rev. 3.00 Feb 22, 2006 page 137 of 624
REJ09B0281-0300