H8S-2668 Datasheet, PDF (113/667 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 5 Interrupt Controller
5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK)
IPR are eleven 16-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts
other than NMI.
The correspondence between interrupt sources and IPR settings is shown in table 5.2 (Interrupt
Sources, Vector Addresses, and Interrupt Priorities). Setting a value in the range from H'0 to H'7
in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 sets the priority of the corresponding
interrupt. IPR should be read in word size.
Bit Bit Name Initial Value R/W
15
—
0
—
14
IPR14
1
R/W
13
IPR13
1
R/W
12
IPR12
1
R/W
11
—
0
—
10
IPR10
1
R/W
9
IPR9
1
R/W
8
IPR8
1
R/W
Description
Reserved
This bit is always read as 0 and cannot be
modified.
Sets the priority of the corresponding interrupt
source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
Reserved
This bit is always read as 0 and cannot be
modified.
Sets the priority of the corresponding interrupt
source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
Rev. 3.00 Feb 22, 2006 page 73 of 624
REJ09B0281-0300