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| R1QGA7236ABB Datasheet, PDF (17/39 Pages) Renesas Technology Corp – 72-Mbit QDRII+ SRAM 4-word Burst | |||
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Common
R1GAA72 / R1QKA72 Series
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit Notes
Input voltage on any ball
VIN
â0.5 to VDD + 0.5
(2.5 V max.)
V
1, 4
Input/output voltage
VI/O
â0.5 to VDDQ + 0.5
(2.5 V max.)
V
1, 4
Core supply voltage
Output supply voltage
Junction temperature
VDD
VDDQ
Tj
â0.5 to 2.5
â0.5 to VDD
+125 (max)
V
1, 4
V
1, 4
°C
5
Storage temperature
Notes:
TSTG
â55 to +125
°C
1. All voltage is referenced to VSS.
2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
Functional operation should be restricted the Operation Conditions. Exposure to higher than
recommended voltages for extended periods of time could affect device reliability.
3. These CMOS memory circuits have been designed to meet the DC and AC specifications
shown in the tables after thermal equilibrium has been established.
4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF
then VIN. Remember, according to the Absolute Maximum Ratings table, VDDQ is not to
exceed 2.5 V, whatever the instantaneous value of VDDQ.
5. Some method of cooling or airflow should be considered in the system. (Especially for high
frequency or ODT parts)
Recommended DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit Notes
Power supply voltage -- core
Power supply voltage -- I/O
Input reference voltage -- I/O
Input high voltage
Input low voltage
Notes:
VDD
VDDQ
VREF
VIH (DC)
VIL (DC)
1.7
1.4
0.68
VREF + 0.1
â0.3
1.8
1.5
0.75
â¯
â¯
1.9
VDD
0.95
VDDQ + 0.3
VREF â 0.1
V
1
V
1, 2
V
3
V 1, 4, 5
V 1, 4, 5
1. At power-up, VDD and VDDQ are assumed to be a linear ramp from 0V to VDD(min.) or
VDDQ(min.) within 200ms. During this time VDDQ < VDD and VIH < VDDQ.
During normal operation, VDDQ must not exceed VDD.
2. Please pay attention to Tj not to exceed the temperature shown in the absolute maximum
ratings table due to current from VDDQ.
3. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF.
4. These are DC test criteria. The AC VIH / VIL levels are defined separately to measure timing
parameters.
5. Overshoot: VIH (AC) ⤠VDDQ + 0.5 V for t ⤠tKHKH/2
Undershoot: VIL (AC) ⥠â0.5 V for t ⤠tKHKH/2
During normal operation, VIH(DC) must not exceed VDDQ and VIL(DC) must not be lower than VSS.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
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