R1QGA7236ABB Datasheet, PDF (11/39 Pages) Renesas Technology Corp – 72-Mbit QDRII+ SRAM 4-word Burst

IIP
R1GAA72 / R1QKA72 Series
QVLD (Valid data indicator)
(R1QA, R1QB, R1QC, R1QD, R1QE, R1QF, R1QG, R1QH, R1QJ, R1QK, R1QL, R1QM
R1QN, R1QP series)
1. QVLD is provided on the QDR-II+ and DDR-II+ to simplify data capture on high speed systems. The Q
Valid indicates valid output data. QVLD is activated half cycle before the read data for the receiver to be
ready for capturing the data. QVLD is inactivated half cycle before the read finish for the receiver to stop
capturing the data. QVLD is edge aligned with CQ and /CQ.
ODT (On Die Termination)
(R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series)
1. To reduce reflection which produces noise and lowers signal quality, the signals should be terminated,
especially at high frequency. Renesas offers ODT on the input signals to QDR-II+ and DDR-II+ family of
devices. (See the ODT pin table)
2. In ODT enable devices, the ODT termination values tracks the value of RQ. The ODT range is selected by
ODT control input. (See the ODT range table)
3. In DDR-II+ devices having common I/O bus, ODT is automatically enabled when the device inputs data
and disabled when the device outputs data.
4. There is no difference in AC timing characteristics between the SRAMs with ODT and SRAMs without
ODT.
5. There is no increase in the I_DD of SRAMs with ODT, however, there is an increase in the I_DDQ (current
consumption from the I/O voltage supply) with ODT.
ODT range
ODT control pin
Thevenin equivalent resistance (R_THEV)
Option 1
Option 2
Unit
-
Notes
6
Low
0.3 × RQ
(ODT disable)
Ω
1, 4
High
0.6 × RQ
0.6 × RQ
Ω
2, 5
Floating
0.6 × RQ
(ODT disable)
Ω
3
Notes:
1. Allowable range of RQ for Option 1 to guarantee impedance matching a tolerance of ± 20 % is
175 Ω ” RQ ” 350 Ω.
2. Allowable range of RQ to guarantee impedance matching a tolerance of ± 20 % is
175 Ω ” RQ ” 250 Ω.
3. Allowable range of RQ for Option 1 to guarantee impedance matching a tolerance of ± 20 % is
175 Ω ” RQ ” 250 Ω.
4. At option 1, ODT control pin is connected to V_DDQ through 3.5 kΩ. Therefore it is recommended
to connect it to V_SS through less than 100 Ω to make it low.
5. At option 2, ODT control pin is connected to V_SS through 3.5 kΩ. Therefore it is recommended to
connect it to V_DDQ through less than 100 Ω to make it high.
6. Renesas status: Option 1 = Available, Option 2 = Possible. If you need devices with option 2,
please contact Renesas sales office.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011