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R1Q4A7236ABB_15 Datasheet, PDF (17/36 Pages) Renesas Technology Corp – 72-Mbit DDRII SRAM 2-word Burst
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Common
R1Q4A7236ABB / R1Q4A7218ABB Series
Leakage Currents & Output Voltage
Parameter
Symbol
Min
Max
Unit Test condition Notes
Input leakage current
Output leakage current
Output high voltage
ILI
ILO
VOH
(Low)
VOH
−2
−5
VDDQ − 0.2
VDDQ/2
− 0.12
2
5
VDDQ
VDDQ/2
+ 0.12
μA
10
μA
11
V |IOH| ≤ 0.1 mA 8, 9
V
Note 6
8, 9
Output low voltage
VOL
(Low)
VOL
VSS
VDDQ/2
− 0.12
0.2
VDDQ/2
+ 0.12
V
IOL ≤ 0.1 mA 8, 9
V
Note 7
8, 9
Notes:
1. All inputs (except ZQ, VREF) are held at either VIH or VIL.
2. IOUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min.
3. Operating supply currents (IDD) are measured at 100% bus utilization. IDD of QDR family is current of
device with 100% write and 100% read cycle. IDD of DDR family is current of device with 100% write
cycle (if IDD(Write) > IDD(Read)) or 100% read cycle (if IDD(Write) < IDD(Read)).
4. All address / data inputs are static at either VIN > VIH or VIN < VIL.
5. Reference value. (Condition = NOP currents are valid when entering NOP after all pending READ and
WRITE cycles are completed. )
6. Outputs are impedance-controlled. |IOH| = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
7. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
8. AC load current is higher than the shown DC values. AC I/O curves are available upon request.
9. HSTL outputs meet JEDEC HSTL Class I and Class II standards.
10. 0 ≤ VIN ≤ VDDQ for all input balls (except VREF, ZQ, TCK, TMS, TDI ball).
If R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series, balls with ODT do not follow this spec.
11. 0 ≤ VOUT ≤ VDDQ (except TDO ball), output disabled.
Rev. 0.11 : 2013.01.15
R10DS0166EJ0011
PAGE:17
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