R1Q4A7236ABB_15 Datasheet, PDF (11/36 Pages) Renesas Technology Corp – 72-Mbit DDRII SRAM 2-word Burst

R1Q4A7236ABB / R1Q4A7218ABB Series
K Truth Table
Operation
K /LD R-/W
DQ
Write Cycle:
Load address, input write
data on consecutive K
Ĺ
and /K rising edges
Data in
LL
Input
data
Input
clock
D(A1)
K(t+1)Ĺ
D(A2)
/K(t+1)Ĺ
Data out
Read Cycle:
Load address, output
read data on consecutive
Ĺ
C and /C rising edges
Output
data
Q(A1)
L
H _{Input RL*8=1.5}
/C(t+1)Ĺ
clock RL=2.0
C(t+2)Ĺ
for Q _RL=2.5
/C(t+2)Ĺ
Q(A2)
C(t+2)Ĺ
/C(t+2)Ĺ
C(t+3)Ĺ
NOP (No operation)
Ĺ
H × High-Z
Standby (Clock stopped) Stopped × × Previous state
Notes:
1. H: high level, L: low level, ×: don’t care, Ĺ: rising edge.
2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C
rising edges, except if C and /C are high, then data outputs are delivered at K and /K rising
edges.
3. /LD and R-/W must meet setup/hold times around the rising edges (low to high) of K and are
registered at the rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. When clocks are stopped, the following cases are recommended; the case of K = low, /K =
high, C = low and /C = high, or the case of K = high, /K = low, C = high and /C = low. This
condition is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
7. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal
burst address in accordance with the linear burst sequence.
8. RL = Read Latency (unit = cycle).
Burst Sequence
Linear Burst Sequence Table (R1Q4Aww36 / R1Q4Aww18 series )
SA0
SA0
External address
0
1
1st internal burst address
1
0
Notes
Rev. 0.11 : 2013.01.15
R10DS0166EJ0011
PAGE:11