HD49340NP_15 Datasheet, PDF (16/24 Pages) Renesas Technology Corp – CDS/PGA & 10-bit A/D Converter

HD49340NP/HNP
• Clamp (D3 to D7 of register 2)
Determine the OB part level with digital code of ADC output.
Clamp level = setting data × 2 + 14
Default data is 9 = 32 LSB.
• HGstop-Hsel, HGain-Nsel (D8 to D11 of register 2)
Determine the lead-in speed of OB clamp. Details are referred to page 6. PGA gain need to be changed for switch
the high speed leading mode. Transfer the gain +1/–1 to previous field, its switch to high speed leading mode.
• Low_PWR (D12 of register 2)
Switch circuit current and frequency characteristic.
Data = 0: 36 MHz guarantee
Data = 1: 25 MHz guarantee
• SPinv (D13 of register 2)
SPSIG/SPBLK/PBLK input signal inverted switching.
Data = 1: Normal
Data = 0: Inverted
• Reset (D15 of register 2)
Software reset.
Data = 1: Normal
Data = 0: Reset
Offset calibration should be done when starting up with using this bit. Details are referred to page 18.
• C_Bias_off (D3 of register 3)
Center bias is turned off in ADCIN mode.
Data = 0: Normally on
Data = 1: Off
• Ave_4H (D6 of register 3)
Clamp detection data is averaged 4H.
Data = 0: 1H
Data = 1: Averaged 4H
Differential Code and Gray Code (D4 to D5 and D7 to D9 of register 3)
• Gray code (D4 to D5 of register 3)
DC output code can be change to following type.
Gray Code [1] Gray Code [0] Output Code
0
0
Binary code
0
1
Gray code
1
0
Differential encoded binary
1
1
Differential encoded gray
• Serial data setting items (D7 to D9 of register 3)
Setting Bit
Setting Contents
Gray_test[0]
Standard data output timing control signal
Gray_test[1]
(Refer to the following table)
Gray_test[2]
ADCLK polar with OBP. (Lo→Positive edge, HI→Negative edge)
• Standard data output timing
Gray_test[1] Gray_test[0]
Low
Low
Low
High
High
Low
High
High
Standard Data Output Timing
Third and fourth
Fourth and fifth
Fifth and sixth
Sixth and seventh
Rev.1.0 Apr 20, 2004 page 14 of 21