HD49335F_15 Datasheet, PDF (16/32 Pages) Renesas Technology Corp – CDS/PGA & 10-bit A/D TG Converter

HD49335F/HF
Absolute Maximum Ratings
Item
Symbol
Ratings
Power supply voltage
VDD
Analog input voltage
VIN
Digital input voltage
VI
Operating temperature range
Ta
4.1
–0.3 to AVDD +0.3
–0.3 to DVDD +0.3
–20 to +85
Power dissipation
Pt
590
Storage temperature
Tstg
–55 to +125
Power supply voltage
Vopr
2.70 to 3.30
Note:
AVDD, AVSS are analog power source systems of CDS, PGA, and ADC.
DVDD1, DVSS1 are digital power source systems of CDS, PGA and ADC.
DVDD2, DVSS2 are buffer power source systems of ADC output.
DVDD3, DVSS3 are general digital power source systems of TG.
DVDD4, DVSS4 are buffer power source systems of H1 and H2.
• Pin 2 multi bonds the DVSS1 and DVSS2
• When pin 64 is set to Low, pin 41 = STROB output, pin 39 = SUB_SW output
When Hi, pin 41 = Vgate input, pin 39 = ADCK input
(Ta = 25°C)
Unit
V
V
V
°C
mW
°C
V
Electrical Characteristics
(Unless othewide specified, Ta = 25°C, AV_DD = 3.0 V, DV_DD = 3.0 V, and R_BIAS = 33 kΩ)
• Items Common to CDSIN and ADCIN Input Modes
Item
Symbol Min
Typ
Max
Unit
Test Conditions Remarks
Power supply voltage
range
Conversion frequency
Digital input voltage
VDD
2.70
3.00
fCLK hi
fCLK low
VIH2
20
—
5.5
—
2.25
×
DV_DD
3.0
—
3.30
36
25
DVDD
V
MHz
MHz
V
LoPwr = low *²
LoPwr = high *²
HD49335HF
HD49335F
CS, SCK, SDATA
VIL2
0
—
0.6
×
DV_DD
3.0
V
Digital output voltage
VOH
DVDD –0.5
—
—
VOL
—
—
0.5
Digital input current
IIH
—
—
50
IIL
–50
—
—
ADC resolution
RES
10
10
10
V
IOH = –1 mA
V
IOL = +1 mA
µA
VIH = 3.0 V
µA
VIL = 0 V
bit
ADC integral linearity
ADC differential linearity+
ADC differential linearity–
Sleep current
INL
DNL+
DNL–
ISLP
—
—
–0.99
–100
(2)
—
0.3
0.99
–0.3
—
0
100
LSBp-p fCLK = 25 MHz
LSB
fCLK = 25 MHz
*1
LSB
fCLK = 25 MHz
*1
µA
Digital input pin is
set to 0 V, output
pin is open
Standby current
ISTBY
—
3
5
mA
Digital I/O pin is set
to 0 V
Notes: 1. Differential linearity is the calculated difference in linearity errors between adjacent codes.
2. 2 divided mode: fCLK = 1/2CLK_in
3 divided mode: fCLK = 1/3CLK_in
3. Values within parentheses ( ) are for reference.
Rev.1.0, Feb.25.2004, page 14 of 29