HD49330AF_15 Datasheet, PDF (16/22 Pages) Renesas Technology Corp – CDS/PGA & 12-bit A/D Converter

HD49330AF/AHF
Absolute Maximum Ratings
(Ta = 25°C)
Item
Symbol
Ratings
Unit
Power supply voltage
VDD(max)
4.1
V
Analog input voltage
VIN(max)
–0.3 to AVDD +0.3
V
Digital input voltage
VI(max)
–0.3 to DVDD +0.3
V
Operating temperature
Topr
–10 to +75
°C
Power dissipation
Pt(max)
400
mW
Storage temperature
Tstg
–55 to +125
°C
Power supply voltage range
Vopr
2.85 to 3.3
V
Notes: 1. VDD indicates AVDD and DVDD.
2. AVDD and DVDD must be commonly connected outside the IC. When they are separated by a noise filter, the
potential difference must be 0.3 V or less at power on, and 0.1 V or less during operation.
Electrical Characteristics
(Unless othewide specified, Ta = 25°C, AV_DD = 3.0 V, DV_DD = 3.0 V, and R_BIAS = 33 kΩ)
• Items Common to CDSIN and ADCIN Input Modes
Item
Symbol Min
Typ
Max
Unit
Test Conditions Remarks
Power supply voltage
VDD
2.85
3.0
3.3
V
range
Conversion frequency
Digital input voltage
fCLK low 5.5
—
fCLK hi
20
—
VIH
2.0
×
DV_DD
3.0
—
VIL
0
—
20
36
DVDD
0.8
×
DV_DD
3.0
MHz
MHz
V
V
LoPwr = high
LoPwr = low
Digital input pins
other than CS,
SCK and SDATA
VIH2
2.25
×
DV_DD
3.0
—
DVDD
V
CS, SCK, SDATA
VIL2
0
—
0.6
×
DV_DD
3.0
V
Digital output voltage
VOH
DVDD –0.5
—
—
VOL
—
—
0.5
Digital input current
IIH
—
—
50
IIH2
—
—
250
IIL
–50
—
—
Digital output current
IOZH
—
—
50
IOZL
–50
—
—
ADC resolution
RES
12
12
12
V
IOH = –1 mA
V
IOL = +1 mA
µA
VIH = 3.0 V
µA
VIH = 3.0 V
µA
VIL = 0 V
µA
VOH = VDD
µA
VOL = 0 V
bit
ADC integral linearity
ADC differential linearity+
ADC differential linearity–
Sleep current
INL
DNL+
DNL–
ISLP
—
—
–0.95
–100
(8)
—
0.6
0.95
–0.6
—
0
100
LSBp-p fCLK = 20 MHz
LSB
fCLK = 20 MHz
*1
LSB
fCLK = 20 MHz
*1
µA
Digital input pin is
set to 0 V, output
pin is open
Standby current
ISTBY
—
3
5
mA
Digital I/O pin is set
to 0 V
Digital output Hi-Z
delay time
tHZ
—
tLZ
—
tZH
—
tZL
—
—
100
—
100
—
100
—
100
ns
RL = 2 kΩ,
ns
CL = 10 pF
ns
ns
See figure 7
Notes: 1. Differential linearity is the calculated difference in linearity errors between adjacent codes.
2. Values within parentheses ( ) are for reference.
Rev.1.0, Apr.05.2004, page 14 of 19