HD49330AF_15 Datasheet, PDF (14/22 Pages) Renesas Technology Corp – CDS/PGA & 12-bit A/D Converter

HD49330AF/AHF
Detailed Timing Specifications at Pre-Blanking
Figure 5 shows the pre-blanking detailed timing specifications.
PBLK
Vth
Digital output ADC
(D0 to D11) data
Clamp level
V_OH
ADC
data
t_PBLK
ADCLK × 2 clocks
V_OL
ADCLK × 12 clocks
(shifts one clock cycle depending
on the PBLK input timing)
When serial data SPinv bit is set to low
(When the SPinv is set to high, the PBLK polarity is inverted.)
Figure 5 Detailed Timing Specifications at Pre-Blanking
Detailed Timing Specifications when ADCIN Input Mode is Used
Figure 6 shows the detailed timing chart when ADCIN input mode is used, and table 9 shows each timing specification.
ADCIN
(2)
ADCLK
D0 to D11
(1)
(3)
(4)
(5)
Vth
V_DD/2
Figure 6 Detailed Timing Chart when ADCIN Input Mode is Used
Table 9 Timing Specifications when ADCIN Input Mode is Used
No.
(1)
(2), (3)
(4)
(5)
Timing
Signal fetch time
ADCLK tWH min./tWL min.
ADCLK rising to digital output hold time
ADCLK rising to digital output delay time
Symbol
tADC1
tADC2, 3
tAHLD4
tAOD5
Min
—
Typ × 0.85
10
—
Typ
(6)
1/2fADCLK
14.5
23.5
Max
—
Typ × 1.15
—
31.5
Unit
ns
ns
ns
ns
Detailed Timing Specifications for Digital Output-Enable Control
Figure 7 shows the detailed timing specifications for digital output enable control. When the OEB pin is set to high,
output disable mode is entered, and the output state becomes High-Z.
OEB Vth
Digital output
t_LZ
(D0 to D11)
t_HZ
DV_DD/2
t_ZL
DV_DD/2
t_ZH
DV_DD
V_OL
V_OH
DV_SS
t_LZ, t_ZL
measurement load
DV_DD
2 kΩ
10 pF
DV_SS
t_HZ, t_ZH
measurement load
10 pF 2 kΩ
DV_SS DV_SS
Figure 7 Detailed Timing Specifications for Digital Output Enable Control
Rev.1.0, Apr.05.2004, page 12 of 19