RMHE41A184AGBG Datasheet, PDF (15/52 Pages) Renesas Technology Corp – 1.1G-BIT Low Latency DRAM-III Common I/O Burst Length of 4

RMHE41A184AGBG, RMHE41A364AGBG
Datasheet
Parameter
Any QK to any DQ, DINV
Any QK to any DQ, DINV
Any QK to QVLD
Any QK to QVLD
QK to DQ output driver turn-on time
and ODT turn-on time
QK to DQ output driver turn-off time
and ODT turn-on time
DQ to RST# setup
DQ to RST# hold
RST# pulse length
RST# deasserted to CS# or LBK# asserted
Time for PLL to stabilize after being
enabled
MRS command start to next CS#, or LBK#
assertion; also from previous command
to MRS command
Symbol
tQKQ
tQH
tQKQV
tQVH
tQON
–120
( 800 MHz )
MIN.
MAX.
0. 150
0.35*
0. 150
0.85*
0.100
–150
( 667 MHz )
MIN.
MAX.
0.180
0.35*
0.180
0.85*
0.120
(2/2)
Unit Note
ns
9
tCK(avg)
5
ns
tCK(avg)
5
ns
tQOFF
–0.1*
0.100
–0.1*
0.120
ns
5
tCK(avg)
tCK(avg)
tRDS
1000 *
1000 *
tCK
2
tRDH
5*
5*
tCK
1
tRSS
200
200
µs
tRSH
400000 *
400000 *
tCK
tPLL
20
20
µs
tMRD
24 *
24 *
tCK
Notes 1. All input hold timing assumes rising edge slew rate of 2 V/ns measured from VIL/VIH (DC) to VREF.
2. All input setup timing assumes falling edge slew rate of 2 V/ns measured from VREF to VIL/VIH (AC)
3. All output timing assumes the load shown in Figure 1-6.
4. Setup/hold windows, tASH, tCSH, tISH are used for de-skew timing budgeting and are based on electrical
simulations. These cannot be directly measured without performing de-skew training.
5. tCK (avg) is the value of tCK averaged over 200 clock cycles.
6. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
7. Frequency drift is not allowed.
8. The cumulative jitter error, tERR(nper), where n is the number of clocks between 2 and 50, is the amount of clock
time allowed to accumulate consecutively away from the average clock over n number of clock cycles.
9. tQKQ, tQKQ0 and tQKQ1 are guaranteed by design.
Figure 1-6 Output Load
VDDQ
Output
50 Ω
60 Ω
2 pF
R10DS0250EJ0100 Rev. 1.00
Jun. 19, 2015
Page 15 of 51