PD46364092B_15 Datasheet, PDF (15/36 Pages) Renesas Technology Corp – 36M-BIT DDR II SRAM 2-WORD BURST OPERATION

μPD46364092B, μPD46364182B, μPD46364362B
DC Characteristics 2 (TA = -40 to 85°C, V_DD = 1.8 ± 0.1 V)
Parameter
Symbol
Test condition
Input leakage current
ILI
I/O leakage current
ILO
Operating supply current
IDD
(Read cycle / Write cycle)
VIN ≤ VIL or VIN ≥ VIH, -E33Y
II/O = 0 mA,
Cycle = MAX.
-E40Y
MIN.
−2
−2
MAX.
Unit Note
x9 x18 x36
+2
μA
+2
μA
570 600 640 mA
540 560 600
Standby supply current
(NOP)
Output HIGH voltage
Output LOW voltage
ISB1
VOH(Low)
VOH
VOL(Low)
VOL
VIN ≤ VIL or VIN ≥ VIH, -E33Y
II/O = 0 mA,
Cycle = MAX.
-E40Y
Inputs static
|IOH| ≤ 0.1 mA
Note1
IOL ≤ 0.1 mA
Note2
510 530 550 mA
490 500 520
V_DDQ−0.2
V_DDQ/2−0.12
V_SS
V_DDQ/2−0.12
V_DDQ
V_DDQ/2+0.12
0.2
V_DDQ/2+0.12
V 3, 4
V 3, 4
V 3, 4
V 3, 4
Notes 1. Outputs are impedance-controlled. | I_OH | = (V_DDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
2. Outputs are impedance-controlled. I_OL = (V_DDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
3. AC load current is higher than the shown DC values.
4. HSTL outputs meet JEDEC HSTL Class I standards.
R10DS0091EJ0400 Rev.4.00
Nov 09, 2012
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