PD46364092B_15 Datasheet, PDF (11/36 Pages) Renesas Technology Corp – 36M-BIT DDR II SRAM 2-WORD BURST OPERATION

μPD46364092B, μPD46364182B, μPD46364362B
Byte Write Operation
[μPD46364092B]
Operation
K
K#
Write DQ0 to DQ8
L→H
−
−
L→H
Write nothing
L→H
−
−
L→H
Remarks 1. H : HIGH, L : LOW, → : rising edge.
BW0#
0
0
1
1
2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
[μPD46364182B]
Operation
Write DQ0 to DQ17
Write DQ0 to DQ8
Write DQ9 to DQ17
Write nothing
K
L→H
−
L→H
−
L→H
−
L→H
−
K#
−
L→H
−
L→H
−
L→H
−
L→H
BW0#
0
0
0
0
1
1
1
1
BW1#
0
0
1
1
0
0
1
1
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[μPD46364362B]
Operation
Write DQ0 to DQ35
Write DQ0 to DQ8
Write DQ9 to DQ17
Write DQ18 to DQ26
Write DQ27 to DQ35
Write nothing
K
L→H
−
L→H
−
L→H
−
L→H
−
L→H
−
L→H
−
K#
−
L→H
−
L→H
−
L→H
−
L→H
−
L→H
−
L→H
BW0#
0
0
0
0
1
1
1
1
1
1
1
1
BW1#
0
0
1
1
0
0
1
1
1
1
1
1
BW2#
0
0
1
1
1
1
0
0
1
1
1
1
BW3#
0
0
1
1
1
1
1
1
0
0
1
1
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
R10DS0091EJ0400 Rev.4.00
Nov 09, 2012
Page 11 of 35