H8S-2144B Datasheet, PDF (14/546 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

10.3.5 Timer Control/Status Register (TCSR)................................................................. 235
10.3.6 Timer Input Select Register (TISR)...................................................................... 240
10.4 Operation ........................................................................................................................... 240
10.4.1 Pulse Output ......................................................................................................... 240
10.5 Operation Timing............................................................................................................... 242
10.5.1 TCNT Count Timing ............................................................................................ 242
10.5.2 Timing of CMFA and CMFB Setting at Compare-Match .................................... 243
10.5.3 Timing of Timer Output at Compare-Match......................................................... 243
10.5.4 Timing of Counter Clear at Compare-Match........................................................ 244
10.5.5 TCNT External Reset Timing............................................................................... 244
10.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 245
10.6 Operation with Cascaded Connection................................................................................ 246
10.6.1 16-Bit Count Mode ............................................................................................... 246
10.6.2 Compare-Match Count Mode ............................................................................... 247
10.7 Interrupt Sources................................................................................................................ 248
10.8 Usage Notes ....................................................................................................................... 249
10.8.1 Conflict between TCNT Write and Clear ............................................................. 249
10.8.2 Conflict between TCNT Write and Increment...................................................... 250
10.8.3 Conflict between TCOR Write and Compare-Match............................................ 251
10.8.4 Conflict between Compare-Matches A and B ...................................................... 252
10.8.5 Switching of Internal Clocks and TCNT Operation ............................................. 252
10.8.6 Mode Setting with Cascaded Connection ............................................................. 254
10.8.7 Module Stop Mode Setting ................................................................................... 255
Section 11 Watchdog Timer (WDT) ................................................................... 257
11.1 Features.............................................................................................................................. 257
11.2 Input/Output Pins............................................................................................................... 259
11.3 Register Descriptions......................................................................................................... 259
11.3.1 Timer Counter (TCNT)......................................................................................... 259
11.3.2 Timer Control/Status Register (TCSR)................................................................. 260
11.4 Operation ........................................................................................................................... 264
11.4.1 Watchdog Timer Mode......................................................................................... 264
11.4.2 Interval Timer Mode............................................................................................. 266
11.4.3 RESO Signal Output Timing (Available for H8S/2144B).................................... 267
11.5 Interrupt Sources................................................................................................................ 267
11.6 Usage Notes ....................................................................................................................... 268
11.6.1 Notes on Register Access ..................................................................................... 268
11.6.2 Conflict between Timer Counter (TCNT) Write and Increment........................... 269
11.6.3 Changing Values of CKS2 to CKS0 Bits.............................................................. 269
11.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................. 269
Rev. 1.00 Jun.24, 2005 Page xiv of xxxii