|
3802_M Datasheet, PDF (139/208 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES | |||
|
◁ |
APPENDIX
3.1 Electrical characteristics
3.1.12 Timing requirements and Switching characteristics (Extended operating temperature version)
Table 3.1.19 Timing requirements (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = â40 to 85 °C, unless otherwise noted)
Symbol
Parameter
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twH(INT)
twL(CNTR)
twL(INT)
tc(SCLK1)
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
tsu(RXDâSCLK1)
tsu(SIN2 âSCLK2)
th(SCLK1âRXD)
th(S CLK2âSIN2 )
Reset input âLâ pulse width
External clock input cycle time
External clock input âHâ pulse width
External clock input âLâ pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input âHâ pulse width
INT0 to INT4 input âHâ pulse width
CNTR0, CNTR1 input âLâ pulse width
INT0 to INT4 input âLâ pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input âHâ pulse width (Note)
Serial I/O2 clock input âHâ pulse width
Serial I/O1 clock input âLâ pulse width (Note)
Serial I/O2 clock input âLâ pulse width
Serial I/O1 input set up time
Serial I/O2 input set up time
Serial I/O1 input hold time
Serial I/O2 input hold time
Limits
Unit
Min. Typ. Max.
2
µs
125
ns
50
ns
50
ns
200
ns
80
ns
80
ns
80
ns
80
ns
800
ns
1000
ns
370
ns
400
ns
370
ns
400
ns
220
ns
200
ns
100
ns
200
ns
Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is â1â. Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is â0â.
Table 3.1.20 Switching characteristics (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = â40 to 85 °C, unless otherwise noted)
Symbol
Parameter
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
td(SCLK1âTXD)
td(SCLK2âSOUT2)
tv(SCLK1âTXD)
tv(SCLK2âSOUT2)
tr(SCLK1)
tf(SCLK1)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O1 clock output âHâ pulse width
Serial I/O2 clock output âHâ pulse width
Serial I/O1 clock output âLâ pulse width
Serial I/O2 clock output âLâ pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O2 output delay time (Note 2)
Serial I/O1 output valid time (Note 1)
Serial I/O2 output valid time (Note 2)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
Test conditions
Fig. 3.1.1
Limits
Min.
Typ.
tc(SCLK1)/2â30
tc(SCLK2)/2â160
tc(SCLK1)/2â30
tc(SCLK2)/2â160
â30
0
10
10
Unit
Max.
ns
ns
ns
ns
140 ns
200 ns
ns
ns
30 ns
30 ns
30 ns
40 ns
30 ns
30 ns
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is â0â.
2: When the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is â0â.
3: XOUT pin excluded.
3-12
3802 GROUP USER'S MANUAL
|
▷ |