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| R1QGA4436RBG_15 Datasheet, PDF (13/30 Pages) Renesas Technology Corp – 144-Mbit QDR™II+ SRAM 4-word Burst Architecture (2.0 Cycle Read latency) | |||
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R1QGA4436RBG,R1QGA4418RBG
Bus Cycle State Diagram
Datasheet
/R = H
/R = H & RCount = 4
Read Port NOP /R = L
RInit = 0
Supply voltage
provided
Load New Always
Read Address
RCount = 0
RInit = 1
/R = L
Read Double
RCount
= RCount + 2
&
RCount = 4
RCount
=2
Increment
Read Address
by Two*1
Always
RInit = 0
Power Up
Supply voltage
provided
Write Port NOP
/W = L
RInit = 0
/W = H
Load New Always Write Double
Write Address
WCount = 0
/W = L
WCount
= WCount + 2
&
WCount = 4
/W = H & WCount = 4
WCount
=2
Increment
Write Address
Always
by Two*1
Notes:
1. The address is concatenated with two additional internal LSBs to facilitate burst operation. The address order
is always fixed as: xxxâ¦xxx+0, xxxâ¦xxx+1, xxxâ¦xxx+2, xxxâ¦xxx+3.
Bus cycle is terminated at the end of this sequence (burst count = 4).
2. Read and write state machines can be active simultaneously. Read and write cannot be simultaneously
initiated. Read takes precedence.
3. State machine control timing sequence is controlled by K.
R10DS0139EJ0201 Rev.2.01
Aug 01, 2014
Page 13 of 29
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