TMP102 Datasheet, PDF (12/19 Pages) Burr-Brown (TI) – Low Power Digital Temperature Sensor With SMBus™/Two-Wire Serial Interface in SOT563

TMP102
SBOS397B – AUGUST 2007 – REVISED OCTOBER 2008 ............................................................................................................................................... www.ti.com
TIMING DIAGRAMS
The TMP102 is two-wire and SMBus compatible.
Figure 12 to Figure 15 describe the various
operations on the TMP102. Parameters for Figure 12
are defined in Table 13. Bus definitions are:
Bus Idle: Both SDA and SCL lines remain high.
Start Data Transfer: A change in the state of the
SDA line, from high to low, while the SCL line is high,
defines a START condition. Each data transfer is
initiated with a START condition.
Stop Data Transfer: A change in the state of the
SDA line from low to high while the SCL line is high
defines a STOP condition. Each data transfer is
terminated with a repeated START or STOP
condition.
Data Transfer: The number of data bytes transferred
between a START and a STOP condition is not
limited and is determined by the master device. It is
also possible to use the TMP102 for single byte
updates. To update only the MS byte, terminate the
communication by issuing a START or STOP
communication on the bus.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an Acknowledge
bit. A device that acknowledges must pull down the
SDA line during the Acknowledge clock pulse in such
a way that the SDA line is stable low during the high
period of the Acknowledge clock pulse. Setup and
hold times must be taken into account. On a master
receive, the termination of the data transfer can be
signaled by the master generating a
Not-Acknowledge ('1') on the last byte that has been
transmitted by the slave.
PARAMETER
f_(SCL)
f_(SCL)
t_(BUF)
t_(HDSTA)
t_(SUSTA)
t_(SUSTO)
t_(HDDAT)
t_(SUDAT)
t_(LOW)
t_(LOW)
t_(HIGH)
t_F
t_R
t_R
Table 13. Timing Diagram Definitions
TEST CONDITIONS
SCL Operating Frequency, V_S > 1.7V
SCL Operating Frequency, V_S < 1.7V
Bus Free Time Between STOP and START
Condition
Hold time after repeated START condition.
After this period, the first clock is generated.
Repeated START Condition Setup Time
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Clock Low Period, V_S > 1.7V
SCL Clock Low Period, V_S < 1.7V
SCL Clock High Period
Clock/Data Fall Time
Clock/Data Rise Time
Clock/Data Rise Time for SCLK ≤ 100kHz
FAST MODE
MIN
MAX
0.001
0.4
0.001
0.4
600
100
100
100
0
100
1300
1300
600
300
300
1000
HIGH-SPEED MODE
MIN
MAX
0.001
3.4
0.001
2.75
160
100
100
100
0
10
160
200
60
160
UNIT
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
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