TMP102 Datasheet, PDF (10/19 Pages) Burr-Brown (TI) – Low Power Digital Temperature Sensor With SMBus™/Two-Wire Serial Interface in SOT563

TMP102
SBOS397B – AUGUST 2007 – REVISED OCTOBER 2008 ............................................................................................................................................... www.ti.com
SERIAL INTERFACE
The TMP102 operates as a slave device only on the
two-wire bus and SMBus. Connections to the bus are
made via the open-drain I/O lines SDA and SCL. The
SDA and SCL pins feature integrated spike
suppression filters and Schmitt triggers to minimize
the effects of input spikes and bus noise. The
TMP102 supports the transmission protocol for both
fast (1kHz to 400kHz) and high-speed (1kHz to
3.4MHz) modes. All data bytes are transmitted MSB
first.
SERIAL BUS ADDRESS
To communicate with the TMP102, the master must
first address slave devices via a slave address byte.
The slave address byte consists of seven address
bits, and a direction bit indicating the intent of
executing a read or write operation.
The TMP102 features an address pin to allow up to
four devices to be addressed on a single bus.
Table 12 describes the pin logic levels used to
properly connect up to four devices.
Table 12. Address Pin and Slave Addresses
DEVICE TWO-WIRE
ADDRESS
1001000
1001001
1001010
1001011
A0 PIN CONNECTION
Ground
V+
SDA
SCL
WRITING/READING OPERATION
Accessing a particular register on the TMP102 is
accomplished by writing the appropriate value to the
Pointer Register. The value for the Pointer Register is
the first byte transferred after the slave address byte
with the R/W bit low. Every write operation to the
TMP102 requires a value for the Pointer Register
(see Figure 13).
When reading from the TMP102, the last value stored
in the Pointer Register by a write operation is used to
determine which register is read by a read operation.
To change the register pointer for a read operation, a
new value must be written to the Pointer Register.
This action is accomplished by issuing a slave
address byte with the R/W bit low, followed by the
Pointer Register byte. No additional data are
required. The master can then generate a START
condition and send the slave address byte with the
R/W bit high to initiate the read command. See
Figure 14 for details of this sequence. If repeated
reads from the same register are desired, it is not
necessary to continually send the Pointer Register
bytes, because the TMP102 remembers the Pointer
Register value until it is changed by the next write
operation.
Note that register bytes are sent with the most
significant byte first, followed by the least significant
byte.
SLAVE MODE OPERATIONS
The TMP102 can operate as a slave receiver or slave
transmitter. As a slave device, the TMP102 never
drives the SCL line.
Slave Receiver Mode:
The first byte transmitted by the master is the slave
address, with the R/W bit low. The TMP102 then
acknowledges reception of a valid address. The next
byte transmitted by the master is the Pointer
Register. The TMP102 then acknowledges reception
of the Pointer Register byte. The next byte or bytes
are written to the register addressed by the Pointer
Register. The TMP102 acknowledges reception of
each data byte. The master can terminate data
transfer by generating a START or STOP condition.
Slave Transmitter Mode:
The first byte transmitted by the master is the slave
address, with the R/W bit high. The slave
acknowledges reception of a valid slave address. The
next byte is transmitted by the slave and is the most
significant byte of the register indicated by the Pointer
Register. The master acknowledges reception of the
data byte. The next byte transmitted by the slave is
the least significant byte. The master acknowledges
reception of the data byte. The master can terminate
data transfer by generating a Not-Acknowledge on
reception of any data byte, or generating a START or
STOP condition.
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