R1LP5256E Datasheet, PDF (12/15 Pages) Renesas Technology Corp – 256Kb Advanced LPSRAM (32k word x 8bit)

R1LP5256E Series
Low Vcc Data Retention Characteristics
Parameter
Symbol Min. Typ. Max. Unit
Test conditions^*2
V_CC for data retention
V_DR
2.0
-
5.5
V ^{Vin ≥ 0V}
CS# ≥ Vcc-0.2V
-
1^*1
2
μA ~+25°C
Data retention current
-
-
3
μA ~+40°C _{Vcc=3.0V, Vin ≥ 0V,}
I_CCDR
CS# ≥ Vcc-0.2V
-
-
8
μA ~+70°C
-
-
10 μA ~+85°C
Chip deselect to data retention time t_CDR
0
-
-
ns
See retention waveform.
Operation recovery time
t_R
5
-
-
ms
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
2. CS# controls address buffer, WE# buffer, OE# buffer and Din buffer. If CS# controls data retention mode, Vin
levels (address, WE#, OE#, DQ) can be in the high impedance state.
R10DS0070EJ0100 Rev.1.00
2011.04.13
Page 12 of 13