M66271FP Datasheet, PDF (12/28 Pages) Mitsubishi Electric Semiconductor – OPERATION PANEL CONTROLLER

M66271FP
Description of Cycle Steal
Basic Timing
Basic timing of M66271FP is two clocks of OSC (internal clock after dividing OSC1 input).
Assign first clock to accessing from MPU to VRAM and second clock to transferring of display data from VRAM to
LCD.
OSC
(Internal clock after
dividing OSC1 input)
CP output
(Display data transfer)
Access
from MPU
to VRAM
Data transfer
from VRAM
to LCD
MPU
Basic cycle
Figure 2 Basic Timing
LCD
Operation Cycle of MPU Access (During WAIT Output)
Writing or reading operation for VRAM during cycle steal needs 1 cycle in best case or 3 cycles in worst case,
according to the condition of the internal cycle steal at staring access requested from MPU.
Ex.) Assuming that MCS input is later than RD, LWR and HWR input.
Best case
Cycle of
LCD access
Cycle of
MPU access
MCS
Cycle of
LCD access
Cycle of
MPU access
Cycle of
LCD access
WAIT
Worst case
MCS
MPUCLK
Cancel WAIT, when synchronize
with rising edge of MPUCLK
WAIT
MPUCLK
Cancel WAIT, when synchronize
with rising edge of MPUCLK
Figure 3 Operation Cycle of MPU Access
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
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