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HD74HC192 Datasheet, PDF (12/14 Pages) Hitachi Semiconductor – Synchronous Up/Down Decade,4-bit Binary Counter(Dual Clock Line) | |||
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HD74HC192, HD74HC193
⢠Waveform â 5
tr
tf
90 %
VCC
Clear
50 % 50 %
10 %
10 %
0V
tW
tr
tf
Data
(A to D)
90 %
50 %
90 %
50 %
VCC
50 %
10 %
10 %
0V
tsu
th
tsu
th
tf
90 %
90 %
VCC
Load
50 %
50 %
50 % 50 %
10 %
10 %
0V
tPHL
tPLH
tr
tPHL
90 %
90 %
90 %
VOH
Q
50 %
50 %
50 %
10 %
10 %
10 %
VOL
tTHL
tTLH
tTHL
Notes : 1. Load Input Pulse : PRR ⤠1 MHz, Zo = 50 â¦, tr ⤠6 ns, tf ⤠6 ns
2. Data Input Pulse : PRR ⤠500 kHz, Zo = 50 â¦, tr ⤠6 ns, tf ⤠6 ns
Rev.3.00, Jan 31, 2006 page 12 of 13
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