HD64F3644HV Datasheet, PDF (113/551 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Series

Section 5 Power-Down Modes
Bits 6 to 4Standby Timer Select 2 to 0 (STS2 to STS0): These bits designate the time the
CPU and peripheral modules wait for stable clock operation after exiting from standby mode or
watch mode to active mode due to an interrupt. The designation should be made according to the
clock frequency so that the waiting time is at least 10 ms.
Bit 6: STS2
0
Bit 5: STS1
0
1
1
*
Legend: * Don’t care
Bit 4: STS0
0
1
0
1
*
Description
Wait time = 8,192 states
Wait time = 16,384 states
Wait time = 32,768 states
Wait time = 65,536 states
Wait time = 131,072 states
(initial value)
Bit 3Low Speed on Flag (LSON): This bit chooses the system clock (φ) or subclock (φ_SUB) as
the CPU operating clock when watch mode is cleared. The resulting operation mode depends on
the combination of other control bits and interrupt input.
Bit 3: LSON
0
1
Description
The CPU operates on the system clock (φ)
The CPU operates on the subclock (φSUB)
(initial value)
Bits 2Reserved Bits: Bit 2 is reserved: it is always read as 1 and cannot be modified.
Bits 1 and 0Active (Medium-Speed) Mode Clock Select (MA1, MA0): Bits 1 and 0 choose
φ_osc/128, φ_osc/64, φ_osc/32, or φ_osc/16 as the operating clock in active (medium-speed) mode and
sleep (medium-speed) mode. MA1 and MA0 should be written in active (high-speed) mode or
subactive mode.
Bit 1: MA1
0
1
Bit 0: MA0
0
1
0
1
Description
φosc/16
φosc/32
φosc/64
φosc/128
(initial value)
Rev. 6.00 Sep 12, 2006 page 91 of 526
REJ09B0326-0600