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R1LP0408D_17 Datasheet, PDF (11/13 Pages) Renesas Technology Corp – 4Mb Advanced LPSRAM | |||
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R1LP0408D Series
Low Vcc Data Retention Characteristics
Parameter
VCC for data retention
Symbol Min. Typ. Max. Unit
Test conditions*3
VDR
2.0
â
5.5
V
Vin ⥠0V,
CS# ⥠Vcc-0.2V
â 0.8*1 2.5 ïA ~+25°C
Data retention current
â
1*2
3
ïA ~+40°C
ICCDR
Vcc=3.0V, Vin ⥠0V,
CS# ⥠Vcc-0.2V
â
â
8
ïA ~+70°C
â
â
10 ïA ~+85°C
Chip deselect time to data retention
tCDR
Operation recovery time
tR
0
5
â
â
â
â
ns
ms
See retention waveform.
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.
2. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=40ºC), and not 100% tested.
3. CS# controls address buffer, WE# buffer, OE# buffer and Din buffer. If data retention mode, Vin levels
(address, WE#, OE#, I/O) can be in the high impedance state.
Low Vcc Data Retention Timing Waveforms
CS# Controlled
Vcc
2.2V
tCDR
CS#
4.5V 4.5V
tR
VDR
2.2V
CS# ⥠Vcc - 0.2V
R10DS0274EJ0100 Rev.1.00
2017.1.27
Page 11 of 11
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