R1LP0108E_17 Datasheet, PDF (11/13 Pages) Renesas Technology Corp – 1Mb Advanced LPSRAM

R1LP0108E Series
Low Vcc Data Retention Characteristics
Parameter
VCC for data retention
Symbol Min. Typ. Max. Unit
Test conditions^*2
Vin ≥ 0V,
VDR
2.0
-
5.5
V ^{(1) 0V ≤ CS2 ≤ 0.2V or}
(2) CS1# ≥ Vcc-0.2V,
CS2 ≥ Vcc-0.2V
Data retention current
ICCDR
-
0.6^*1
2
-
-
3
-
-
8
A ~+25°C
Vcc=3.0V, Vin ≥ 0V,
A ~+40°C
(1) 0V ≤ CS2 ≤ 0.2V or
(2) CS1# ≥ Vcc-0.2V,
A ~+70°C
CS2 ≥ Vcc-0.2V
-
-
10 A ~+85°C
Chip deselect time to data retention
tCDR
0
Operation recovery time
tR
5
-
-
-
-
ns
ms
See retention waveform.
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
2. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer and Din buffer. If CS2 controls data
retention mode, Vin levels (address, WE#, CS1#, OE#, DQ) can be in the high impedance state.
If CS1# controls data retention mode, CS2 must be CS2 ≥ Vcc-0.2V or 0V ≤ CS2 ≤ 0.2V. The other input
levels (address, WE# ,OE#, DQ) can be in the high impedance state.
Low Vcc Data Retention Timing Waveforms
(1) CS1# Controlled
Vcc
t_CDR
2.2V
CS1#
4.5V 4.5V
t_R
V_DR
CS1# ≥ Vcc - 0.2V
2.2V
(2) CS2 Controlled
Vcc
CS2
t_CDR
0.2V
4.5V 4.5V
t_R
V_DR
0V ≤ CS2 ≤ 0.2V
0.2V
R10DS0270EJ0100 Rev.1.00
2017.1.27
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