M5M29KE131BTP Datasheet, PDF(11/33 Page) Renesas Technology Corp – 134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT) CMOS FLASH MEMORY

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M5M29KE131BTP Datasheet, PDF (11/33 Pages) Renesas Technology Corp – 134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT) CMOS FLASH MEMORY

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Renesas LSIs

M5M29KE131BTP

134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)

CMOS FLASH MEMORY

Stacked-uMCP (micro Multi Chip Package)

Software Command Definition

Command List (WP# =VIH or VIL)

Com m and

Read Array

Page Read

Device Identifier

Read Status Register

Clear Status Register

Mode

Write

1st Bus Cycle

Address

Data1)

(DQ0-15)(DQ0-7)

A227)

A0-A21=X8)

A227)

A0-A21=X8)

FFH

F3H

A22=VIL

A0-A21=X8)

Bank2)

A227)

A0-A21=X8)

90H

70H

50H

Mode

Read

2nd Bus Cycle

Addres s

Data1)

Mode

A22-A18 A0 (DQ0-15)(DQ0-7)

SA5)

A22=VIL IA3)

Bank2)

RD0

SRD4)

Read

3rd-5th Bus Cycle

Address

Data1)

(DQ0-15)(DQ0-7)

SA+i6)

RDi

Suspend

Resume

Write

Bank2)

B0H

D0H

1) In the case of Word mode(BYTE#=VIH), upper byte data (DQ15-DQ8) is ignored.

2) Bank=Bank address (Bank(I)-Bank(VIII): A22-18)

3) IA=ID code address: A0=VIL (Manufacturerâs code): A0=VIH (Device code), ID=ID code

4) SRD=Status Register Data

5) SA=A21-A2:1st Page Address, A1,A0:voluntary address / RD0=1st Page read data

6) SA+i: Page address(is equal to 1st Page Address of A21-A2), A1,A0: voluntary address / RDi: 2nd Page read data

7) In case of Bottom 64M-bit area, A22 must be set to VIL.

In case of Top 64M-bit area, A22 must be set to VIH.

8) X can be VIH or VIL.

Command List (WP# =VIH)

Command

Word Program

Page Program

Page Buffer to Flash

Block Erase/Confirm

Erase All Unlocked Blocks

Clear Page Buffer

Single Data Load to Page Buffer

Flash to Page Buffer

1st Bus Cycle

Mode

Write

Address

Bank7)

A228)

A0-A21=X9)

A228)

A0-A21=X9)

A228)

A0-A21=X9)

Bank7)

Data1)

(DQ0-15)(DQ0-7)

40H

41H

0EH

20H

A7H

Mode

Write

55H

Write

74H

Write

F1H

Write

2nd Bus Cycle

3rd-129th Bus Cycles

3rd-257th Bus Cycles(Byte mode)

Address

WA2)

WA03)

WA4)

BA5)

A228)

A0-A21=X9)

A228)

A0-A21=X9)

WA2)

Data1)

(DQ0-15)(DQ0-7)

WD2)

WD03)

D0H1)

WD2)

Mode Address

Data1)

(DQ0-15)(DQ0-7)

Write WAn3)

WDn3)

RA6)

D0H1)

1) In the case of Word mode(BYTE#=VIH), upper byte data (DQ15-DQ8) is ignored.

2) WA=Write Address, WD=Write Data

3) WA0, WAn=Write Address, WD0, WDn=Write Data.

Word mode (BYTE#=VIH) : Write address and write data must be provided sequentially from 00H to 7FH for A6-A0. Page size is 128

words (128-word x 16-bit), and also A22-A7 (block address, page address) must be valid.

Byte mode (BYTE#=VIL) : Write address and write data must be provided sequentially from 00H to FFH for A6-A-1. Page size is 256

Bytes (256-byte x 8-bit), and also A22-A7 (block address, page address) must be valid.

4) WA=Write Address: A22-A7 (block address, page address) must be valid.

5) BA=Block Address : A22-A12[Bank(I),Bank(VIII)], A22-A15 [Bank(II) ~ Bank(VII)]

6) RA=Read Address: A22-A7 (block address, page address) must be valid.

7) Bank=Bank address (Bank(I)-Bank(VIII): A22-18)

8) In case of Bottom 64M-bit area, A22 must be set to VIL. In case of Top 64M-bit area, A22 must be set to VIH.

9) X can be VIH or VIL.

Rev.1.1_48a_bezz

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