HD74LV161A_15 Datasheet, PDF (11/18 Pages) Renesas Technology Corp – Synchronous 4-bit Binary Counter (Direct Clear)

HD74LV161A
Switching Characteristics (cont)
Item
Maximum clock
frequency
Propagation
delay time
Setup time
Symbol
fmax
t_PLH/t_PHL
t_PLH/t_PHL
Count mode
t_PLH/t_PHL
Load mode
t_PLH/t_PHL
t_PHL
t_PHL
t_su
Ta = 25°C
Min Typ
135 185
95 125
— 4.9
— 8.7
— 4.9
— 6.4
— 6.2
— 7.7
— 4.9
— 6.4
— 5.5
— 7.0
— 5.0
— 6.5
4.5 —
5.0 —
5.0 —
1.5 —
Hold time
t_h
Pulse width
t_w
1.0 —
5.0 —
5.0 —
Max
—
—
8.1
10.1
8.1
10.1
10.3
12.3
8.1
10.1
9.0
11.0
8.6
10.6
—
—
—
—
—
—
—
Ta = –40 to 85°C
Min
Max
115
—
85
—
1.0
9.5
1.0
11.5
1.0
9.5
1.0
11.5
1.0
12.0
1.0
14.0
1.0
9.5
1.0
11.5
1.0
10.5
1.0
12.5
1.0
10.0
1.0
12.0
4.5
—
6.0
—
6.0
—
1.5
—
1.0
—
5.0
—
5.0
—
Unit
MHz
ns
ns
ns
ns
Test
Conditions
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
V_CC = 5.0 ± 0.5 V
FROM TO
(Input) (Output)
CLK
Q
CLK
Carry
CLK
Carry
ENT
Carry
CLR
Q
CLR
Carry
Data before CLK ↑
LOAD before CLK ↑
ENT, ENP before
CLK ↑
CLR inactive before
CLK ↑
CLK H or L
CLR L
Operating Characteristics
C_L = 50 pF
Ta = 25°C
Item
Symbol V_CC (V) Min
Typ
Max
Unit Test Conditions
Power dissipation capacitance C_PD
3.3
—
5.0
—
17.0
—
20.4
—
pF
f = 10 MHz
Rev.4.00 Jun. 04, 2004 page 9 of 15