R8C2G Datasheet, PDF (106/344 Pages) Renesas Technology Corp – MCU

R8C/2G Group
10. Bus
10. Bus
The bus cycles differ when accessing ROM/RAM, and when accessing SFR.
Table 10.1 lists Bus Cycles by Access Space of the R8C/2G Group.
ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are
accessed twice in 8-bit units.
Table 10.2 lists Access Units and Bus Operations.
Table 10.1
SFR
ROM/RAM
Bus Cycles by Access Space of the R8C/2G Group
Access Area
Bus Cycle
2 cycles of CPU clock
1 cycle of CPU clock
Table 10.2 Access Units and Bus Operations
Area
SFR
Even address
Byte access
CPU clock
Address
Data
Even
Data
Odd address
Byte access
CPU
clock
Address
Data
Odd
Data
Even address
Word access
CPU
clock
Address
Data
Even
Data
Even + 1
Data
Odd address
Word access
CPU
clock
Address
Data
Odd
Data
Odd + 1
Data
CPU
clock
Address
Data
CPU
clock
Address
Data
CPU
clock
Address
Data
CPU
clock
Address
Data
ROM, RAM
Even
Data
Odd
Data
Even
Data
Even + 1
Data
Odd
Data
Odd + 1
Data
Rev.1.00 Apr 04, 2008 Page 86 of 318
REJ09B0387-0100