H836109 Datasheet, PDF (101/622 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Tiny Series

Section 4 Address Break
Initial
Bit
Bit Name Value
1
DCMP1 0
0
DCMP0 0
[Legend]
x: Don't care.
R/W Description
R/W Data Compare 1 and 0
R/W These bits set the comparison condition between the
data set in BDR and the internal data bus.
00: No data comparison
01: Compares lower 8-bit data between BDRL and
data bus
10: Compares upper 8-bit data between BDRH and
data bus
11: Compares 16-bit data between BDR and data bus
When an address break is set in the data read cycle or data write cycle, the data bus used will
depend on the combination of the byte/word access and address. Table 4.1 shows the access and
data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a
byte access is generated twice. For details on data widths of each register, see section 22.1,
Register Addresses (Address Order).
Table 4.1 Access and Data Bus Used
ROM space
RAM space
I/O register with
8-bit data bus width
I/O register with
16-bit data bus width
Word Access
Even Address Odd Address
Upper 8 bits
Lower 8 bits
Upper 8 bits
Lower 8 bits
Upper 8 bits
Upper 8 bits
Upper 8 bits
Lower 8 bits
Byte Access
Even Address Odd Address
Upper 8 bits Upper 8 bits
Upper 8 bits Upper 8 bits
Upper 8 bits Upper 8 bits
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Rev. 1.50 Sep. 18, 2007 Page 67 of 584
REJ09B0240-0150