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| RMLV0816BGBG_15 Datasheet, PDF (10/15 Pages) Renesas Technology Corp – 8Mb Advanced LPSRAM (512k word × 16bit) | |||
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RMLV0816BGBG - 4S2
Write Cycle (3) (CS1#, CS2 CLOCK)
A0~18
CS1#
CS2
tWC
Valid address
tAW
tAS
tCW
tWR
tAS
tCW
LB#,UB#
WE#
tBW
tWP *25
OE#
VIH
OE# = âHâ level
DQ0~15
tDW
tDH
VVaalliiddDDaattaa
Note
25. tWP is the interval between write start and write end.
A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.
R10DS0229EJ0100 Rev.1.00
2014.11.28
Page 10 of 13
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