R1QAA3636CBB Datasheet, PDF (10/38 Pages) Renesas Technology Corp – 36-Mbit QDR II+ SRAM 4-word Burst

Common
R1QAA36**C / R1QDA36**C Series
DLL/PLL Constraints
1. DLL/PLL uses K clock as its synchronizing input. The input should have low phase jitter which is
specified as tKC var.
2. The lower end of the frequency at which the DLL/PLL can operate is 120 MHz.
(Please refer to AC Characteristics table for detail.)
3. When the operating frequency is changed or /DOFF level is changed, setup cycles are required again.
Programmable Output Impedance
1. Output buffer impedance can be programmed by terminating the ZQ ball to V_SS through a precision resistor
(RQ). The value of RQ is five times the output impedance desired. The allowable range of RQ to
guarantee impedance matching with a tolerance of 15% is 250 : typical. The total external capacitance of
ZQ ball must be less than 7.5 pF.
Rev. 0.10b : 2012.03.12
R10DS0192EJ0010
PAGE : 10