M5M5T5672TG Datasheet, PDF (1/24 Pages) Renesas Technology Corp – 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

Preliminary
Notice: This is not final specification.
Some parametric limits are subject to change.
DESCRIPTION
The M5M5T5672TG is a family of 18M bit synchronous SRAMs
organized as 262144-words by 72-bit. It is designed to eliminate
dead bus cycles when turning the bus around between reads
and writes, or writes and reads. Renesas's SRAMs are
fabricated with high performance, low power CMOS technology,
providing greater reliability. M5M5T5672TG operates on a single
2.5V power supply and are 2.5V CMOS compatible.
FEATURES
• Fully registered inputs and outputs for pipelined operation
• Fast clock speed: 200 MHz
• Fast access time: 3.2 ns
• Single 2.5V –5% and +5% power supply VDD
• Individual byte write (BWa# - BWh#) controls may be tied
LOW
• Single Read/Write control pin (W#)
• Snooze mode (ZZ) for power down
• Linear or Interleaved Burst Modes
• JTAG boundary scan support
APPLICATION
High-end networking products that require high bandwidth, such
as switches and routers.
Renesas LSIs
M5M5T5672TG – 20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
FUNCTION
Synchronous circuitry allows for precise cycle control triggered
by a positive edge clock transition.
Synchronous signals include : all Addresses, all Data Inputs,
all Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV),
Byte Write Enables (BWa#, BWb#, BWc#, BWd#, BWe#, BWf#,
BWg#, BWh#) and Read/Write (W#).
Write operations are controlled by the eight Byte Write
Enables (BWa# - BWh#) and Read/Write(W#) inputs. All writes
are conducted with on-chip synchronous self-timed write
circuitry.
Asynchronous inputs include Output Enable (G#), Clock (CLK)
and Snooze Enable (ZZ).
The HIGH input of ZZ pin puts the SRAM in the power-down
state.
The Linear Burst order (LBO#) is DC operated pin. LBO# pin
will allow the choice of either an interleaved burst, or a linear
burst.
All read, write and deselect cycles are initiated by the ADV
Low input. Subsequent burst address can be internally
generated as controlled by the ADV HIGH input.
PACKAGE
M5M5T5672TG
Bump
209(11X19) bump BGA
Body Size
14mm X 22mm
Bump Pitch
1mm
PART NAME TABLE
Part Name
M5M5T5672TG -20
Access
3.2ns
Cycle
5.0ns
Active Current
(max.)
450mA
Standby Current
(max.)
30mA
1/24
Preliminary
M5M5T5672TG-20 REV.1.0