HD74LV2GT125A Datasheet, PDF (1/9 Pages) Renesas Technology Corp – Dual Bus Buffer with 3-state Output / CMOS Logic Level Shifter

HD74LV2GT125A
Dual Bus Buffer with 3–state Output /
CMOS Logic Level Shifter
REJ03D0148–0200Z
(Previous ADE-205-676A (Z))
Rev.2.00
Oct.23.2003
Description
The HD74LV2GT125A has dual bus buffer with 3–state output in an 8 pin package. Output is disabled
when the associated output enable (OE) input is high. To ensure the high impedance state during power up
or power down, OE should be connected to V_CC through a pull-up resistor; the minimum value of the
resistor is determined by the current sinking capability of the driver. The input protection circuitry on this
device allows over voltage tolerance on the input, allowing the device to be used as a logic–level translator
from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while
operating at the high-voltage power supply. Low voltage and high-speed operation is suitable for the
battery powered products (e.g., notebook computers), and the low power consumption extends the battery
life.
Features
• The basic gate function is lined up as Renesas uni logic series.
• Supplied on emboss taping for high-speed automatic mounting.
• TTL compatible input level.
Supply voltage range : 3.0 to 5.5 V
Operating temperature range : –40 to +85°C
• Logic-level translate function
3.0 V CMOS logic → 5.0 V CMOS logic (@V_CC = 5.0 V)
1.8 V or 2.5 V CMOS logic → 3.3 V CMOS logic (@V_CC = 3.3 V)
• All inputs V_IH (Max.) = 5.5 V (@V_CC = 0 V to 5.5 V)
All outputs V_O (Max.) = 5.5 V (@V_CC = 0 V, Output : Z)
• Output current ±6 mA (@V_CC = 3.0 V to 3.6 V), ±12 mA (@V_CC = 4.5 V to 5.5 V)
• All the logical input has hysteresis voltage for the slow transition.
• Ordering Information
Part Name
Package Type
HD74LV2GT125AUSE SSOP-8 pin
Package Code
TTP-8DBV
Package
Abbreviation
US
Taping Abbreviation
(Quantity)
E (3,000 pcs/reel)
Rev.2.00, Oct.23.2003, page 1 of 1