HD74LS163A Datasheet, PDF (1/12 Pages) Hitachi Semiconductor – Synchronous 4-bit Binary Counters(synchronous clear)

HD74LS163A
Synchronous 4-bit Binary Counter (direct clear)
REJ03D0447–0200
Rev.2.00
Feb.18.2005
This synchronous 4-bit binary counter features an internal carry look-ahead for application in high-speed counting
designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs changes
coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation
eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A
buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. This
counter is fully programmable; that is, the output may be preset to either level. As presetting is synchronous, setting up
a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock
pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input would be avoided when the
clock is low if the enable inputs are high at or before the transition. The clear function is asynchronous and a low level
at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable
inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired
can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously
clear the counter to LLLL. Low-to-high transitions at the clear input should be avoided when the clock is low if the
enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading
counters for n-bit synchronous applications without additional getting. Instrumental in accomplishing this function are
two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input
T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output
pulse with a duration approximately equal to the high-level portion of the Q_A output. This high-level overflow ripple
carry pulse can be used to enable successive cascaded stages. High-to-low-level transitions at the enable P or T inputs
should occur only when the clock input is high.
Features
• Ordering Information
Part Name
Package Type
Package Code Package
(Previous Code) Abbreviation
HD74LS163AP
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
P
HD74LS163AFPEL SOP-16 pin (JEITA)
PRSP0016DH-B _FP
(FP-16DAV)
HD74LS163ARPEL SOP-16 pin (JEDEC)
PRSP0016DG-A
(FP-16DNV)
RP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Rev.2.00, Feb.18.2005, page 1 of 11