HD74LS160A Datasheet, PDF (1/11 Pages) Hitachi Semiconductor – Synchronous Decade Counters(direct clear)

HD74LS160A
Synchronous Decade Counter (direct clear)
REJ03D0444–0300
Rev.3.00
Jul.15.2005
This synchronous decade counter features an internal carry look ahead for application in high-speed counting designs.
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs changes
coincident with each other when so instructed by the count-enable inputs and internal gating. This mode is operation
eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A
buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. This
counter is fully programmable; that is, the output may be preset to either level. As presetting is synchronous, setting up
a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock
pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of this device should be
avoided when the clock is low if the enable inputs are high at or before the transition. The clear function is
asynchronous and a low level at the clear input sets all four of the flip-flop outputs. The carry look-ahead circuitry
provides for cascading counters for n-bit synchronous applications without additional getting. Instrumental in
accomplishing this function is two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T)
must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled
will produced a high-level output pulse with a duration approximately equal to the high-level portion of the Q_A output.
This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low-level
transitions at the enable P or T inputs should occur only when the clock input is high.
Features
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74LS160AP
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
P
PRSP0016DH-B
HD74LS160AFPEL SOP-16 pin (JEITA)
(FP-16DAV)
FP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
Pin Arrangement
Clear 1
Clock ²
A3
B4
Data
Inputs _{C 5}
D6
Enable P ⁷
GND 8
CLR
CK ^Ripple
Carry
A
QA
B
QB
C
QC
D
QD
P
T
Load
(Top view)
16 V_CC
15
Ripple
Carry Output
14 _QA
13 _QB
Outputs
12 _QC
11 _QD
10 _{Enable T}
9 _Load
Rev.3.00, Jul.15.2005, page 1 of 10