HD74HCT237 Datasheet, PDF (1/8 Pages) Hitachi Semiconductor – 3-to-8-line Decoder/Demultiplexer with Address Latch

HD74HCT237
3-to-8-line Decoder/Demultiplexer with Address Latch
REJ03D0660–0200
(Previous ADE-205-548)
Rev.2.00
Mar 30, 2006
Description
The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes
from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains
high no address changes will be recognized. Output enable controls, G₁ and G₂, control the state of the outputs
independently of the select or latch-enable inputs.
All of the outputs are high unless G₁ is high and G₂ is low. The HD74HCT137 is ideally suited for the implementation
of glitch free decoders in stored-address applications in bus oriented systems.
Features
• High Speed Operation: t_pd (A, B, C to Y) = 16.5 ns typ (C_L = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: V_CC = 2 V to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: I_CC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HCT237RPEL
SOP-16 pin (JEDEC)
PRSP0016DG-A
(FP-16DNV)
RP
Taping Abbreviation
(Quantity)
EL (2,500 pcs/reel)
Function Table
Inputs
Enable
Select
GL
G₁
G₂
C
B
A
X
X
H
X
X
X
X
L
X
X
X
X
L
H
L
L
L
L
L
H
L
L
L
H
L
H
L
L
H
L
L
H
L
L
H
H
L
H
L
H
L
L
L
H
L
H
L
H
L
H
L
H
H
L
L
H
L
H
H
H
H
H
L
X
X
X
H : High level
L : Low level
X : Irrelevant
Outputs
Y₀
Y₁
Y₂
Y₃
Y₄
Y₅
Y₆
Y₇
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
Output Corresponding to stored address L; all others H
Rev.2.00 Mar 30, 2006 page 1 of 7