English
Language : 

HD74HC323 Datasheet, PDF (1/6 Pages) Hitachi Semiconductor – 8-bit Universal Shift/Storage Register (with 3-state Outputs)
HD74HC323
8-bit Universal Shift/Storage Register (with 3-state Outputs)
REJ03D0610-0200
(Previous ADE-205-489)
Rev.2.00
Jan 31, 2006
Description
This eight-bit universal register features multiplexed I/O ports to achieve full eight bit data handling in a single 20-pin
package. HD74HC323 applications are as stacked or push-down registers, buffer storage, and accumulator registers.
Two function-select inputs and two output control inputs can be used to choose the modes of operation listed in the
function table.
Synchronous parallel loading is accomplished by taking both function-select lines S0 and S1 high. This places the three-
state outputs in a high-impedance state, which permits data that is applied on the I/O ports to be clocked into the
register. Reading out of this register can be accomplished while the outputs are enabled in any mode. The clear
function is synchronous, and a low level at the clear input clears the register on the next low-to-high transition of the
clock.
Features
• High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HC323RPEL SOP-20 pin (JEDEC) PRSP0020DC-A RP
(FP-20DBV)
Taping Abbreviation
(Quantity)
EL (1,000 pcs/reel)
Function Table
Inputs
Function
Mode
Clear Select
Output
Control Clock
Serial
Inputs/Outputs
Outputs
S1
S0 G1† G2†
SL SR A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH QA’ QH’
Clear L
X
L
L
L
X
X
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
L
L
L
L
L
L
L
L
L
Hold H
L
L
L
L
X
X
X
QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0
HX
X
L
L
L
X
X
QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0
Shift H
L
H
L
L
Right H
L
H
L
L
X
H
H
QAn QBn QCn QDn QEn QFn QGn
H
QGn
X
L
L
QAn QBn QCn QDn QEn QFn QGn
L
QGn
Shift H H
L
L
L
Left
HH
L
L
L
H
X
QBn QCn QDn QEn QFn QGn QHn
H
QBn
H
L
X
QBn QCn QDn QEn QFn QGn QHn
L
QBn
L
Load H H H X X
X
X
a
b
c
d
e
f
g
h
a
h
a ... h = the level of the steady-state input at A through H, respectively. These data are loaded into the flip-flops while the
flip-flop outputs are isolated from the input/output terminals.
Rev.2.00 Jan 31, 2006 page 1 of 5
 ▷