HD74AC165 Datasheet, PDF (1/7 Pages) Hitachi Semiconductor – Parallel-Load 8-bit Shift Register

HD74AC165
Parallel-Load 8-bit Shift Register
REJ03D0254–0200Z
(Previous ADE-205-374 (Z))
Rev.2.00
Jul.16.2004
Description
This 8-bit serial shift register shifts data from Q_A to Q_H when clocked, Parallel inputs to each stage are enabled by a low
level at the Shift/Load Input. Also included is a gated clock input and a complementary output from the eighth bit.
Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit function.
Holding either of the clock inputs high inhibits clocking, and holding either clock input low with the Shift/Load input
high enables the other clock input. Data transfer occurs on the positive going edge of the clock. Parallel loading is
inhibited as long as the Shift/Load input is high. When taken low, data at the parallel inputs is loaded directly into the
register independent of the state of the clock.
Features
• Outputs Source/Sink 24 mA
• Ordering Information
Part Name
Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity)
HD74AC165FPEL SOP-16 pin (JEITA) FP-16DAV
FP
EL (2,000 pcs/reel)
HD74AC165RPEL SOP-16 pin (JEDEC) FP-16DNV
RP
EL (2,500 pcs/reel)
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Pin Arrangement
SL 1
CP 2
E3
Parallel ^{F 4}
Inputs
G5
H6
QH 7
GND 8
(Top view)
16 VCC
15
Clock
Inhibit
14 D
13 C _Parallel
Inputs
12 B
11 A
10 SI
9 QH
Rev.2.00, Jul.16.2004, page 1 of 6