R1621 Datasheet, PDF (3/4 Pages) RDC Semiconductor – FAST ETHERNET RISC PROCESSOR

RDC®
RISC DSP Communication
2. Block Diagram
R1621
FAST ETHERNET RISC PROCESSOR
CLKOUTA
INT6-INT5
INT2
INT1
INT0
VCC
GND
X1
X2
Clock and
Power
Management
Interrupt
Control Unit
Timer Control
Unit
RST_n
MCS_n
UCS_n
PCS5_n
PCS3_n
PCS2_n
PCS0_n
Chip
Select
Unit
ARDY
Refresh
Control
Unit
Cache
Instruction
Queue (64bits)
Instruction
Decoder
Control Signal
Register
File
General,
Segment,
Eflag Register
Micro
ROM
EA / LA
Address
SD_CLK
WE_n
CAS_n
RAS_n
BA[1:0]
SDRAM/Bus
Interface
Unit
ALU
(Special,
Logic,
Adder,
BSF)
Execution
Unit
A[19:0]
BHE_n
RD_n
D[15:0]
ALE WR_n/BWSEL
DRQ0 DRQ1
DMA
Unit
MAC1
MII 1
MAC0
PIO
Unit
16550 UART
Serial
Port0
16550 UART
Serial
Port1
MII 0
PIO[39:0]
DCD0_n
SIN0
DSR0_n
CTS0_n
RI0_n
RTS0_n
SOUT0
DTR0_n
DCD1_n
SIN1
DSR1_n
CTS1_n
RI1_n
RTS1_n
SOUT1
DTR1_n
Specifications subject to change without notice, contact your sales representatives for the most update information.
Page 3 of 4
REV 1.0 Aug. 18 2005